src/cmd/compile/internal/ssa/_gen/AMD64.rules | 4 ---- src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules | 5 +++++ src/cmd/compile/internal/ssa/_gen/ARM64.rules | 62 ----------------------------------------------------- src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/cmd/compile/internal/ssa/rewrite.go | 6 +++--- src/cmd/compile/internal/ssa/rewriteAMD64.go | 33 --------------------------------- src/cmd/compile/internal/ssa/rewriteAMD64latelower.go | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/cmd/compile/internal/ssa/rewriteARM64.go | 726 ----------------------------------------------------- src/cmd/compile/internal/ssa/rewriteARM64latelower.go | 748 +++++++++++++++++++++++++++++++++++++++++++++++++++++ test/fixedbugs/issue66066.go | 41 +++++++++++++++++++++++++++++++++++++++++ diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules index aac6873d2888e4c60ce2c54e2360a304ed473a08..2a4c59ebfc7176028ed9bd5eefa83f11b1a81a23 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules @@ -1020,10 +1020,6 @@ (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLQSXload [off] {sym} ptr mem) (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload [off] {sym} ptr mem) (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload [off] {sym} ptr mem) -(MOVLQZX x) && zeroUpper32Bits(x,3) => x -(MOVWQZX x) && zeroUpper48Bits(x,3) => x -(MOVBQZX x) && zeroUpper56Bits(x,3) => x - // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQZX x) (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQZX x) diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules index a1e63d6249ac8a10f4b6a4c30f8475af569b9c87..1dd804577aeafacb704c3ee28e134f6105cc8a3e 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules @@ -6,3 +6,8 @@ // Prefer SARX/SHLX/SHRX instruction because it has less register restriction on the shift input. (SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y) (SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y) (SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) + +// See comments in ARM64latelower.rules for why these are here. +(MOVLQZX x) && zeroUpper32Bits(x,3) => x +(MOVWQZX x) && zeroUpper48Bits(x,3) => x +(MOVBQZX x) && zeroUpper56Bits(x,3) => x diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64.rules b/src/cmd/compile/internal/ssa/_gen/ARM64.rules index c5ee0285d9dbd2bf107064d5c5c74733ade5d6ea..18a6586fb0bf01621489ef7733dd14ecd49d4b29 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64.rules @@ -1054,61 +1054,6 @@ (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) -// don't extend after proper load -(MOVBreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHload _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x) -(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x) - -// fold double extensions -(MOVBreg x:(MOVBreg _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHreg x:(MOVBreg _)) => (MOVDreg x) -(MOVHreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHreg x:(MOVHreg _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) -(MOVWreg x:(MOVBreg _)) => (MOVDreg x) -(MOVWreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVWreg x:(MOVHreg _)) => (MOVDreg x) -(MOVWreg x:(MOVWreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) - // don't extend before store (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem) (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) @@ -1572,17 +1517,10 @@ (GreaterEqualF (InvertFlags x)) => (LessEqualF x) (LessThanNoov (InvertFlags x)) => (CSEL0 [OpARM64NotEqual] (GreaterEqualNoov x) x) (GreaterEqualNoov (InvertFlags x)) => (CSINC [OpARM64NotEqual] (LessThanNoov x) (MOVDconst [0]) x) -// Boolean-generating instructions (NOTE: NOT all boolean Values) always -// zero upper bit of the register; no need to zero-extend -(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => (MOVDreg x) - // Don't bother extending if we're not using the higher bits. (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x - -// omit unsign extension -(MOVWUreg x) && zeroUpper32Bits(x, 3) => x // omit sign extension (MOVWreg (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst x [c]) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules index d0c2099da9b7c3397134ae817ca3d3b4c125fa65..e50d985aa0c8f71d8d49114f48677e66ff451b64 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules @@ -19,3 +19,69 @@ (CMNconst [c] x) && !isARM64addcon(c) => (CMN x (MOVDconst [c])) (CMNWconst [c] x) && !isARM64addcon(int64(c)) => (CMNW x (MOVDconst [int64(c)])) (ADDSconstflags [c] x) && !isARM64addcon(c) => (ADDSflags x (MOVDconst [c])) + +// These rules remove unneeded sign/zero extensions. +// They occur in late lower because they rely on the fact +// that their arguments don't get rewritten to a non-extended opcode instead. + +// Boolean-generating instructions (NOTE: NOT all boolean Values) always +// zero upper bit of the register; no need to zero-extend +(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => x + +// omit unsigned extension +(MOVWUreg x) && zeroUpper32Bits(x, 3) => x + +// don't extend after proper load +(MOVBreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHload _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x) +(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x) + +// fold double extensions +(MOVBreg x:(MOVBreg _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHreg x:(MOVBreg _)) => (MOVDreg x) +(MOVHreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHreg x:(MOVHreg _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) +(MOVWreg x:(MOVBreg _)) => (MOVDreg x) +(MOVWreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVWreg x:(MOVHreg _)) => (MOVDreg x) +(MOVWreg x:(MOVWreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go index bb09c6cddaae2d972a45a12cd02c7f938720cc68..531c5e4cb2c2318c2c4b2e4f93cdb7d7a34edd9d 100644 --- a/src/cmd/compile/internal/ssa/rewrite.go +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -1294,7 +1294,7 @@ case OpARM64REV16W, OpARM64REVW, OpARM64RBITW, OpARM64CLZW, OpARM64EXTRWconst, OpARM64MULW, OpARM64MNEGW, OpARM64UDIVW, OpARM64DIVW, OpARM64UMODW, OpARM64MADDW, OpARM64MSUBW, OpARM64RORW, OpARM64RORWconst: return true - case OpArg: + case OpArg: // note: but not ArgIntReg return x.Type.Size() == 4 case OpPhi, OpSelect0, OpSelect1: // Phis can use each-other as an arguments, instead of tracking visited values, @@ -1318,7 +1318,7 @@ func zeroUpper48Bits(x *Value, depth int) bool { switch x.Op { case OpAMD64MOVWQZX, OpAMD64MOVWload, OpAMD64MOVWloadidx1, OpAMD64MOVWloadidx2: return true - case OpArg: + case OpArg: // note: but not ArgIntReg return x.Type.Size() == 2 case OpPhi, OpSelect0, OpSelect1: // Phis can use each-other as an arguments, instead of tracking visited values, @@ -1342,7 +1342,7 @@ func zeroUpper56Bits(x *Value, depth int) bool { switch x.Op { case OpAMD64MOVBQZX, OpAMD64MOVBload, OpAMD64MOVBloadidx1: return true - case OpArg: + case OpArg: // note: but not ArgIntReg return x.Type.Size() == 1 case OpPhi, OpSelect0, OpSelect1: // Phis can use each-other as an arguments, instead of tracking visited values, diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index 5332512f2af681a4674fcedf1c2febe033f68e8f..ba71189703ddffa6d432eb991ff63dbba7bd1cb0 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -9640,17 +9640,6 @@ v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } - // match: (MOVBQZX x) - // cond: zeroUpper56Bits(x,3) - // result: x - for { - x := v_0 - if !(zeroUpper56Bits(x, 3)) { - break - } - v.copyOf(x) - return true - } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { @@ -10390,17 +10379,6 @@ v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) - return true - } - // match: (MOVLQZX x) - // cond: zeroUpper32Bits(x,3) - // result: x - for { - x := v_0 - if !(zeroUpper32Bits(x, 3)) { - break - } - v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) @@ -12754,17 +12732,6 @@ v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) - return true - } - // match: (MOVWQZX x) - // cond: zeroUpper48Bits(x,3) - // result: x - for { - x := v_0 - if !(zeroUpper48Bits(x, 3)) { - break - } - v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go b/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go index d3dd2633d1044aee762d50e39b8a58755f0efcce..11ecb0b285a22cb6effe8df9188d4374546e48aa 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64latelower.go @@ -6,6 +6,12 @@ import "internal/buildcfg" func rewriteValueAMD64latelower(v *Value) bool { switch v.Op { + case OpAMD64MOVBQZX: + return rewriteValueAMD64latelower_OpAMD64MOVBQZX(v) + case OpAMD64MOVLQZX: + return rewriteValueAMD64latelower_OpAMD64MOVLQZX(v) + case OpAMD64MOVWQZX: + return rewriteValueAMD64latelower_OpAMD64MOVWQZX(v) case OpAMD64SARL: return rewriteValueAMD64latelower_OpAMD64SARL(v) case OpAMD64SARQ: @@ -18,6 +24,51 @@ case OpAMD64SHRL: return rewriteValueAMD64latelower_OpAMD64SHRL(v) case OpAMD64SHRQ: return rewriteValueAMD64latelower_OpAMD64SHRQ(v) + } + return false +} +func rewriteValueAMD64latelower_OpAMD64MOVBQZX(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVBQZX x) + // cond: zeroUpper56Bits(x,3) + // result: x + for { + x := v_0 + if !(zeroUpper56Bits(x, 3)) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64latelower_OpAMD64MOVLQZX(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVLQZX x) + // cond: zeroUpper32Bits(x,3) + // result: x + for { + x := v_0 + if !(zeroUpper32Bits(x, 3)) { + break + } + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64latelower_OpAMD64MOVWQZX(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVWQZX x) + // cond: zeroUpper48Bits(x,3) + // result: x + for { + x := v_0 + if !(zeroUpper48Bits(x, 3)) { + break + } + v.copyOf(x) + return true } return false } diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go index f0a4425502a2b56e5ae62e09412afccbe9ad85f7..8f60f023b18d4986ee98954c41da115212dade6b 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64.go @@ -8307,39 +8307,6 @@ return false } func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVBUreg x:(MOVBUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(MOVBUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVBUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<8-1)] x) for { @@ -8364,160 +8331,6 @@ v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } - // match: (MOVBUreg x:(Equal _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64Equal { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(NotEqual _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64NotEqual { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessThan _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessThan { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessThanU _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessThanU { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessThanF _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessThanF { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessEqual _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessEqual { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessEqualU _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessEqualU { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(LessEqualF _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64LessEqualF { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterThan _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterThan { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterThanU _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterThanU { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterThanF _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterThanF { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterEqual _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterEqual { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterEqualU _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterEqualU { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBUreg x:(GreaterEqualF _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64GreaterEqualF { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVBUreg x) // cond: v.Type.Size() <= 1 // result: x @@ -8748,39 +8561,6 @@ return false } func rewriteValueARM64_OpARM64MOVBreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVBreg x:(MOVBload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBreg x:(MOVBloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVBreg x:(MOVBreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { @@ -10353,83 +10133,6 @@ return false } func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVHUreg x:(MOVBUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVHUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx2 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVBUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHUreg x:(MOVHUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVHUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<16-1)] x) for { @@ -10790,116 +10493,6 @@ return false } func rewriteValueARM64_OpARM64MOVHreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVHreg x:(MOVBload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVBUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVHload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVBloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVBUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVHloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHloadidx2 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVBreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVBUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVHreg x:(MOVHreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { @@ -11955,127 +11548,6 @@ return false } func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVWUreg x:(MOVBUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVHUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVWUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx2 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWUloadidx4 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVBUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVHUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWUreg x:(MOVWUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVWUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<32-1)] x) for { @@ -12106,17 +11578,6 @@ // result: x for { x := v_0 if !(v.Type.Size() <= 4) { - break - } - v.copyOf(x) - return true - } - // match: (MOVWUreg x) - // cond: zeroUpper32Bits(x, 3) - // result: x - for { - x := v_0 - if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) @@ -12428,193 +11889,6 @@ return false } func rewriteValueARM64_OpARM64MOVWreg(v *Value) bool { v_0 := v.Args[0] - // match: (MOVWreg x:(MOVBload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVBUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHUload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVWload _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWload { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVBloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVBUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHUloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVWloadidx _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWloadidx { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHloadidx2 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHUloadidx2 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWloadidx4 { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVBreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVBUreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVBUreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVHreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVHreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } - // match: (MOVWreg x:(MOVWreg _)) - // result: (MOVDreg x) - for { - x := v_0 - if x.Op != OpARM64MOVWreg { - break - } - v.reset(OpARM64MOVDreg) - v.AddArg(x) - return true - } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { diff --git a/src/cmd/compile/internal/ssa/rewriteARM64latelower.go b/src/cmd/compile/internal/ssa/rewriteARM64latelower.go index 09987571855fd16c946ffe5cfe19f5fb2dc13b44..6873fd79968514b92a32243d96b51b57ebbea514 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64latelower.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64latelower.go @@ -18,6 +18,18 @@ case OpARM64CMPWconst: return rewriteValueARM64latelower_OpARM64CMPWconst(v) case OpARM64CMPconst: return rewriteValueARM64latelower_OpARM64CMPconst(v) + case OpARM64MOVBUreg: + return rewriteValueARM64latelower_OpARM64MOVBUreg(v) + case OpARM64MOVBreg: + return rewriteValueARM64latelower_OpARM64MOVBreg(v) + case OpARM64MOVHUreg: + return rewriteValueARM64latelower_OpARM64MOVHUreg(v) + case OpARM64MOVHreg: + return rewriteValueARM64latelower_OpARM64MOVHreg(v) + case OpARM64MOVWUreg: + return rewriteValueARM64latelower_OpARM64MOVWUreg(v) + case OpARM64MOVWreg: + return rewriteValueARM64latelower_OpARM64MOVWreg(v) case OpARM64ORconst: return rewriteValueARM64latelower_OpARM64ORconst(v) case OpARM64SUBconst: @@ -174,6 +186,742 @@ v.reset(OpARM64CMP) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(c) v.AddArg2(x, v0) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVBUreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVBUreg x:(Equal _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64Equal { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(NotEqual _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64NotEqual { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessThan _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessThan { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessThanU _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessThanU { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessThanF _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessThanF { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessEqual _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessEqual { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessEqualU _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessEqualU { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(LessEqualF _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64LessEqualF { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterThan _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterThan { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterThanU _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterThanU { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterThanF _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterThanF { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterEqual _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterEqual { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterEqualU _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterEqualU { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(GreaterEqualF _)) + // result: x + for { + x := v_0 + if x.Op != OpARM64GreaterEqualF { + break + } + v.copyOf(x) + return true + } + // match: (MOVBUreg x:(MOVBUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVBUreg x:(MOVBUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVBreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVBreg x:(MOVBload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVBreg x:(MOVBloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVBreg x:(MOVBreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVHUreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVHUreg x:(MOVBUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVHUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx2 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVBUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHUreg x:(MOVHUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVHreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVHreg x:(MOVBload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVBUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVHload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVBloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVBUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVHloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHloadidx2 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVBreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVBUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVHreg x:(MOVHreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVWUreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVWUreg x) + // cond: zeroUpper32Bits(x, 3) + // result: x + for { + x := v_0 + if !(zeroUpper32Bits(x, 3)) { + break + } + v.copyOf(x) + return true + } + // match: (MOVWUreg x:(MOVBUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVHUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVWUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx2 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWUloadidx4 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVBUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVHUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWUreg x:(MOVWUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + return false +} +func rewriteValueARM64latelower_OpARM64MOVWreg(v *Value) bool { + v_0 := v.Args[0] + // match: (MOVWreg x:(MOVBload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVBUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHUload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVWload _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWload { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVBloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVBUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHUloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVWloadidx _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWloadidx { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHloadidx2 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHUloadidx2 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWloadidx4 { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVBreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVBUreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVBUreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVHreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVHreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) + return true + } + // match: (MOVWreg x:(MOVWreg _)) + // result: (MOVDreg x) + for { + x := v_0 + if x.Op != OpARM64MOVWreg { + break + } + v.reset(OpARM64MOVDreg) + v.AddArg(x) return true } return false diff --git a/test/fixedbugs/issue66066.go b/test/fixedbugs/issue66066.go new file mode 100644 index 0000000000000000000000000000000000000000..a674503b4729b238063471cbad158736afa76fa1 --- /dev/null +++ b/test/fixedbugs/issue66066.go @@ -0,0 +1,41 @@ +// run + +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import "fmt" + +func main() { + testMod() + testMul() +} + +//go:noinline +func mod3(x uint32) uint64 { + return uint64(x % 3) +} + +func testMod() { + got := mod3(1<<32 - 1) + want := uint64((1<<32 - 1) % 3) + if got != want { + fmt.Printf("testMod: got %x want %x\n", got, want) + } + +} + +//go:noinline +func mul3(a uint32) uint64 { + return uint64(a * 3) +} + +func testMul() { + got := mul3(1<<32 - 1) + want := uint64((1<<32-1)*3 - 2<<32) + if got != want { + fmt.Printf("testMul: got %x want %x\n", got, want) + } +}